A digital system can be configured to receive data through a first physical interface, process the data, and then provide that data through a second interface. When the first physical interface is related to a first clock domain and the second physical interface is related to a second clock domain, then the data can cross between clock domains. For example, a digital system can be configured to receive clock and data through a PCIe (Peripheral Component Interconnect Express) Interface and be further configured to provide that data with respect to a second clock domain. In some embodiments, data can be formatted from a serial format (as is the case for PCIe signals) to a parallel format. Moreover, the second clock domain may not have a fundamental frequency in common with the first clock domain that would allow a simple clock divider to be used to provide second clock waveform.
In many embodiments, a digital system can include a relatively accurate clock synthesis portion. The clock synthesis portion can provide a relatively accurate synthesized clock waveform based upon a first clock waveform from the first clock domain. Oftentimes, the design of this clock synthesis block can be complicated requiring relatively large amounts of area (for integrated circuit implementations), relatively large component count (for discrete implementations) and some times relatively large amounts of power.
A problem arises when a particular design cannot support an accurate clock synthesis portion. This circumstance may be the case when approximating a design with a field programmable gate array (FPGA). The FPGA can include some generic clock timing blocks, but may lack relatively accurate and design specific clock waveform generation blocks.
Therefore, what is desired is a simple and low-cost clock synthesis approach for providing an approximation for a clock waveform.